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<title>VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values </title></head>
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<h1>VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>VEX.DDS.128.66.0F38.W0 96 /r</p>
<p>VFMADDSUB132PS xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.128.66.0F38.W0 A6 /r</p>
<p>VFMADDSUB213PS xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.128.66.0F38.W0 B6 /r</p>
<p>VFMADDSUB231PS xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.256.66.0F38.W0 96 /r</p>
<p>VFMADDSUB132PS ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.256.66.0F38.W0 A6 /r</p>
<p>VFMADDSUB213PS ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.256.66.0F38.W0 B6 /r</p>
<p>VFMADDSUB231PS ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.128.66.0F38.W0 A6 /r</p>
<p>VFMADDSUB213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m32bcst and put result in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.128.66.0F38.W0 B6 /r</p>
<p>VFMADDSUB231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.128.66.0F38.W0 96 /r</p>
<p>VFMADDSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, add/subtract elements in zmm2 and put result in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.256.66.0F38.W0 A6 /r</p>
<p>VFMADDSUB213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m32bcst and put result in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.256.66.0F38.W0 B6 /r</p>
<p>VFMADDSUB231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.256.66.0F38.W0 96 /r</p>
<p>VFMADDSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.512.66.0F38.W0 A6 /r</p>
<p>VFMADDSUB213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed single-precision floating-point values from zmm1 and zmm2, add/subtract elements in zmm3/m512/m32bcst and put result in zmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.512.66.0F38.W0 B6 /r</p>
<p>VFMADDSUB231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.512.66.0F38.W0 96 /r</p>
<p>VFMADDSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (r, w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (r, w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>VFMADDSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the corresponding packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the second source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).</p>
<p>VFMADDSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the first source operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the third source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).</p>
<p>VFMADDSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the first source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).</p>
<p>EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-ally updated with write mask k1.</p>
<p>VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.</p>
<p>VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.</p>
<p>Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.</p>
<p><strong>Operation</strong></p>
<p>In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).</p>
<p><strong>VFMADDSUB132PS DEST, SRC2, SRC3</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM -1{</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+31:n] (cid:197)RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])</p>
<p>DEST[n+63:n+32] (cid:197)RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADDSUB213PS DEST, SRC2, SRC3</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM -1{</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+31:n] (cid:197)RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])</p>
<p>DEST[n+63:n+32] (cid:197)RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADDSUB231PS DEST, SRC2, SRC3</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM -1{</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+31:n] (cid:197)RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])</p>
<p>DEST[n+63:n+32] (cid:197)RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)</strong></p>
<p>(KL, VL) (4, 128), (8, 256),= (16, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])</p>
<p>ELSE DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])</p>
<p>FI;</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])</p>
<p>ELSE DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])</p>
<p>FI;</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])</p>
<p>ELSE DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF j *is even*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])</p>
<p>FI;</p>
<p>FI</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VFMADDSUBxxxPS __m512 _mm512_fmaddsub_ps(__m512 a, __m512 b, __m512 c);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, int r);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);</p>
<p>VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);</p>
<p>VFMADDSUBxxxPS __m256 _mm256_mask_fmaddsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);</p>
<p>VFMADDSUBxxxPS __m256 _mm256_maskz_fmaddsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);</p>
<p>VFMADDSUBxxxPS __m256 _mm256_mask3_fmaddsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);</p>
<p>VFMADDSUBxxxPS __m128 _mm_mask_fmaddsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);</p>
<p>VFMADDSUBxxxPS __m128 _mm_maskz_fmaddsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);</p>
<p>VFMADDSUBxxxPS __m128 _mm_mask3_fmaddsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);</p>
<p>VFMADDSUBxxxPS __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);</p>
<p>VFMADDSUBxxxPS __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 2.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E2.</td></tr></table></body></html>